El Vortex86EX es un procesador X86 de alto rendimiento y totalmente estático de 32 bits con la compatibilidad de Windows, Linux y los más populares RTOS de 32 bits. También integra un “Write Through” Cache L1 de 16KB y nivel de asociatividad “4-way”, un “Write Through/ Write Back” Cache L2 de 128KB y nivel de asociatividad “4-way”, PCIE bus a 2.5 GHz, DDR3, controlador ROM, xISA, I2C, SPI, IPC (controladores periféricos internos con DMA y Temporizador de interrupción/contador incluido), Fast Ethernet, FIFO UART, USB2.0 Host y controlador SD/SATA dentro de un solo conjunto de 288 pines LBGA para formar un sistema-en-chip (SOC). Proporciona una solución ideal para que el sistema embebido produzca el rendimiento deseado.
Caracteristicas
x86 32-Bit Processor Core
6 Stage Pipeline
300MHz, 400MHz (Heatsink), 500MHz (Fan)
300MHz, 400MHz (Heatsink), 500MHz (Fan)
FPU Support
Extends CPU instruction set to include Trigonometric, Logarithmic and Exponential
Implements ANSI/IEEE standard 754-1985 for binary Floating-Point Architecture
Implements ANSI/IEEE standard 754-1985 for binary Floating-Point Architecture
Branch Prediction Unit
Branch Target Buffer
Translation Lookaside Buffer
32 I/D Translation Lookaside Buffer
Embedded I / D Separated L1 Cache
16K I-Cache, 16K D-Cache
Embedded L2 Cache
4-way 128KB L2 Cache
Write through or write back policy
Write through or write back policy
DDR2 Control Interface
16 bits data bus
2 rank
DDRIII clock support up to 300MHz
DDRIII size support up to 1GB
2 rank
DDRIII clock support up to 300MHz
DDRIII size support up to 1GB
SD Interface
1 x SD (Primary IDE Channel)
SATA Interface
1 x Sata (Secondary IDE Channel)
MAC Controller + PNY
PCI-E
Supports 1 x PCI-E Slot
PCI-E Target Interface
USB 2.0 Host
2 x USB Ports
Support HS, FS, and LS
Support HS, FS, and LS
USB 1.1 Host
1 x USB 1.1 Port
Supports FS with 3 programmable endpoint
Supports FS with 3 programmable endpoint
HDA Support
Input and Output
ADC Interface
8
I2C bus
Compliant w/t V2.1
Some master code (general call, START and CBUS) not support.
Some master code (general call, START and CBUS) not support.
SPI Boot Interface
For boot up function from SPI flash
Half duplex
Support SPI Flash Size up to 128MB
Half duplex
Support SPI Flash Size up to 128MB
Full Duplex SPI Controller
Some master code (general call, START and CBUS) not support.
Support SPI Device x2 (Chip Select x2)
Support SPI Device x2 (Chip Select x2)
CAN Bus Controller
Motor Control Interface Support