Vortex86DX3

El Vortex86DX3 es un microprocesador dual-core de 32-bit x86-architecture (Dual core by request) con la compatibilidad de Windows, Linux y RTOS de 32 bits más populares.

También integra un cache L1 de tamaño 32KB con modo de operación “Write Through” y nivel de asociatividad “8-way”, un cache L2 de 512KB con “Write Through”/“Write Back” y “4-way”, bus PCIE a 2,5 GHz, DDR3, controlador ROM, ISA, I2C, SPI, IPC (Controladores periféricos internos con DMA e interrupción Temporizador / contador incluido), Fast Ethernet (Rapida), FIFO UART, host USB2.0 y controlador IDE / SATA dentro de un solo paquete de 720 pines BGA para formar un sistema en un chip (SOC). Proporciona una solución ideal para el sistema embebido y productos de comunicaciones (como cliente ligero “Thin Client”, enrutador NAT “NAT router”, puerta de enlace de origen “home gateway”, punto de acceso y Tablet PC) para lograr el rendimiento deseado.

Diagrama de bloques del sistema

Caracteristicas

x86 32-Bit Processor Core

6 Stage Pipe-line

Embedded I/D Separated L1 Cache

16K I-Cache, 16K D-Cache

SDRAM/DDR2 Control Interface

Support DLL for clock phase auto-adjustion

IDE Controller

Support 2 Channels Ultra-DMA 100 (Disk x 4)

LPC (Low Pin Count) Bus Interface

Support 2 Programmable Registers to Decode LPC Addresses

MAC Controller

Supports 1

PCI Controller Interface

Supports Up to 3 Sets of PCI Master Devices
3.3V I/O

ISA Bus Interface

AT Clock Programmable
8/16 Bit ISA Device With Zero-Wait-State
Generate Refresh Signals to ISA Interface During DRAM Refresh Cycle

DMA Controller

Interrupt Controller

Counter/Timers

Supports 2 of 8254 Timer Controllers
Timer Output is 5V Tolerance I/O on 2nd Timer

Real Time Clock (Internal/External)

Below 2uA Power Consumption on Internal Mode (Estimation Value)

FIFO UART 5 x Ports (COM Ports)

Compatible with 16C550/16C552
Default Internal Pull Up
Supports the Programmable Baud Rate Generator with Data Rate from 50kbps to 115.2kbps
The Characters Options are Programmed for 1, 1.5 or 2 stop bits; even, odd or no parity; 5-8 data bits
Supports TXD_EN Signal on COM1/COM2
Port 80H Output Data could be sent to COM1 by software programming.

General Chip Selector

2 Sets of Extended Chip Selector
I/O MAP or Memory MAP could be configurable
I/O Addressing: From 2 byte to 64K byte
Memory Address: From 512 byte to 4G Byte

General Programmable I/O

Support 40 Dedicated Programmable I/O Pins
Each GPIO Pin Can Be Individually Configured to be an Input/Output Pin

USB 2.0 Host

4 x USB Ports
Support HS, FS, and LS

PS/2 Support

Keyboard and Mouse
Compatible with 8042 Controller

Speaker

Output

Embedded 256KB Flash

JTAG Support

Interface Support for S.W Debugging

Input Clock

14.318MHz
32.768KHz

Output Clock

24MHz
25MHz

Operating Voltage Range

Core voltage: 1.2 V ~ 1.4V
I/O voltage: 1.8V ± 5% , 3.3 V ± 10 %

Operating Temperature

-40 – 85 Degrees Celius

Package Type

27 x 27, 581 Balls 8GA

Descargas

F.A.Q

CPU Benchmark Report